PLL synthesizing oscillator with IC 4060B and 4522B Circuit
The IC 4522B is Programmable BCD Counter and IC4060B is 14 Bit binary counter and oscillator. IC4060B has the inverter for the oscillator and the 14-bit binary counter which divides the oscillator output. Make the circuit this time oscillate 4.096 MHz and it is using the output of the 12th bit (1/4096=1KHz) of the binary counter.
This IC has consists of comparing the phase of which detects the difference between the frequency and to compare the frequency and the VCO generates the digital pulses.
There are two types of the phase of the comparison. As for 1, the difference is the phase of the input signal (the frequency and comparison of frequencies), only that the pulse duration (Issue 1). Regarding the 2nd, the difference is the phase of the input signal, the pulse duration and polarity (Issue 2).
The circuit is this time starting with the 2nd
There are two types of the phase of the comparison. As for 1, the difference is the phase of the input signal (the frequency and comparison of frequencies), only that the pulse duration (Issue 1). Regarding the 2nd, the difference is the phase of the input signal, the pulse duration and polarity (Issue 2).
The circuit is this time starting with the 2nd
The VCO can vary by around 1 MHz. Minimum and maximum frequency determined by the value of R4, R5 and C4. Each relational expression is thus as below.
For IC 4522 has the CAS(Cascade feedback) terminal. When this terminal is in the L condition, the “0″ output doesn’t become H.
Because it is, in the dividing of more than one figure, when connecting the “0″ output of the higher rank figure with the CAS terminal of the lower rank, when the subtraction that the higher rank is the number of the specification doesn’t complete, “0″ of the lower rank figure doesn’t become the H condition.
By connecting the Q4 output of the lower rank with the CLOCK terminal of the higher rank, CLOCK of 1/10 is inputted to the higher rank.
Because it is, in the dividing of more than one figure, when connecting the “0″ output of the higher rank figure with the CAS terminal of the lower rank, when the subtraction that the higher rank is the number of the specification doesn’t complete, “0″ of the lower rank figure doesn’t become the H condition.
By connecting the Q4 output of the lower rank with the CLOCK terminal of the higher rank, CLOCK of 1/10 is inputted to the higher rank.
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